1. Field of the Invention
The present invention relates to a semiconductor device having a signal transmission line therein and, more specifically, to a semiconductor memory device having a long I/O line as a signal transmission line. The present invention further relates to a method of driving such signal transmission line or I/O line.
2. Description of the Related Art
Synchronous memory typified by synchronous DRAM (Dynamic Random Access Memory) is widely used in personal computers and the like. Synchronous memory inputs and outputs data synchronously with clock signals supplied from a memory controller, thereby increasing the data transfer rate by using higher clock speeds.
Even in a synchronous DRAM, however, the DRAM core still operates in analog mode. Specifically, a very weak electric charge that is read from the memory cells is amplified by a sense amplifier and is then transmitted to a peripheral circuit area via a hierarchically structured system of I/O lines. It is therefore necessary not only to merely raise the clock frequency to increase memory speed but to also allow the read data that is read from the memory cells to be transmitted more rapidly to a peripheral circuit area in order to increase the data transfer rate.
Local I/O lines for transmitting read data within a memory cell area, as well as main I/O lines for transmitting read data from a memory cell area to a peripheral circuit area, are commonly used as the hierarchically structured I/O lines (See Japanese Patent Laid-open Nos. 2003-7064 and 2005-85289). Among these lines, the main I/O lines are often quite long, having considerable wiring length on the order of several millimeters and therefore take a long time to transmit read data.
Another consideration is that, when a main I/O line is relatively long, the transmission rate may differ considerably depending on the position of the driver circuit used to drive the main I/O line. Specifically, a signal wave form on the main I/O line may degrade and/or distort during transmission along the I/O line depending in part on the location of the driver circuit relative to the point on the I/O line at which the signal is applied, e.g., driver circuits located at a far end of an I/O line versus those located at a near end. Differences in transmission distances and signal degradation and distortion along the I/O line may result in a reduction in the signal quality of read data from the memory.
Such problems are more pronounced in cases in which the main I/O line is a single-ended I/O line. Unlike a differential I/O line in which two complementary signal wires or conductors are used, a single-ended I/O line is composed of a single signal wire. The number of wires can therefore be reduced but, because a single-ended I/O line requires greater electric potential variations than does a differential I/O line, the reduction in the transmission rate becomes more pronounced as the wiring length increases.